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TMS320DM647 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 181 page  TMS320DM647 TMS320DM648 www.ti.com SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009 TMS320DM647/TMS320DM648 Digital Media Processor Check for Samples: TMS320DM647, TMS320DM648 1 Features 1 • Additional Instructions to Support • High-Performance Digital Media Processor Complex Multiplies – 720-MHz, 800-MHz, 900-MHz, 1.1-GHz • C64x+ L1/L2 Memory Architecture C64x+™ Clock Rates – 256K-bit (32K-byte) L1P Program RAM/Cache – 1.39 ns (-720), 1.25 ns (-800), 1.11 ns (-900), [Direct Mapped] 0.91 ns (-1100) Instruction Cycle Time – 256K-bit (32K-byte) L1D Data RAM/Cache – 5760, 6400, 7200, 8800 MIPS [2-Way Set-Associative] – Eight 32-Bit C64x+ Instructions/Cycle – 2M-bit/256K-byte (DM647) or – Fully Software-Compatible With C64x/Debug 4M-Bit/512K-byte) (DM648) L2 Unified – Commercial Temperature Ranges (-720, -900, Mapped RAM/Cache [Flexible Allocation] and -1100 only) • Supports Little Endian Mode Only – Extended Temperature Ranges (-800 only) • Five Configurable Video Ports – Industrial Temperature Ranges (-720, -900, – Providing a Glueless I/F to Common Video and -1100 only) Decoder and Encoder Devices • VelociTI.2™ Extensions to VelociTI™ – Supports Multiple Resolutions/Video Advanced Very-Long-Instruction-Word (VLIW) Standards TMS320C64x+™ DSP Core • VCXO Interpolated Control Port (VIC) – Eight Highly Independent Functional Units – Supports Audio/Video Synchronization With VelociTI.2 Extensions: • External Memory Interfaces (EMIFs) • Six ALUs (32-/40-Bit), Each Supports Single 32-bit, Dual 16-bit, or Quad 8-bit – 32-Bit DDR2 SDRAM Memory Controller With Arithmetic per Clock Cycle 512M-Byte(1) Address Space (1.8-V I/O) • Two Multipliers Support Four 16 x 16-bit – Asynchronous 16-Bit Wide EMIF (EMIFA) Multiplies (32-bit Results) per Clock Cycle • Up to 128M-Byte Total Address Reach or Eight 8 x 8-bit Multiplies (16-Bit • 64M-Byte Address Reach per CE Space Results) per Clock Cycle – Glueless Interface to Asynchronous – Load-Store Architecture With Non-Aligned Memories (SRAM, Flash, and EEPROM) Support – Synchronous Memories (SBSRAM and ZBT – 64 32-bit General-Purpose Registers SRAM) – Instruction Packing Reduces Code Size – Supports Interface to Standard Sync Devices – All Instructions Conditional and Custom Logic (FPGA, CPLD, ASICs, – Additional C64x+™ Enhancements etc.) • Protected Mode Operation • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) • Exceptions Support for Error Detection and Program Redirection • 3-Port Gigabit Ethernet Switch Subsystem • Hardware Support for Modulo Loop • Four 64-Bit General-Purpose Timers (Each Auto-Focus Module Operation Configurable as Two 32-Bit Timers) • C64x+ Instruction Set Features • One UART (With RTS and CTS Flow Control) – Byte-Addressable (8-/16-/32-/64-bit Data) • One 4-wire Serial Port Interface (SPI) With Two Chip-Selects – 8-bit Overflow Protection • Master/Slave Inter-Integrated Circuit (I2C – Bit-Field Extract, Set, Clear Bus™) – Normalization, Saturation, Bit-Counting • Multichannel Audio Serial Port (McASP) – VelociTI.2 Increased Orthogonality – Ten Serializers and SPDIF (DIT) Mode – C64x+ Extensions • Compact 16-bit Instructions (1) From Silicon revision 1.1 and onward. In silicon revision 1.0, the address space is 256M-Bytes. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2010–2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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