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TMS320DM647 Datasheet(PDF) 151 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 151 Page - Texas Instruments |
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151 / 181 page  TMS320DM647 TMS320DM648 www.ti.com SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009 Table 6-72. McASP Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x0204 021A XBUF8 Transmit Buffer for Serializer 8 0x0204 0220 XBUF9 Transmit Buffer for Serializer 9 0x0204 0224-0x0204 027C - Reserved 0x0204 0280 RBUF0 Receive Buffer for Serializer 0 0x0204 0284 RBUF1 Receive Buffer for Serializer 1 0x0204 0288 RBUF2 Receive Buffer for Serializer 2 0x0204 028C RBUF3 Receive Buffer for Serializer 3 0x0204 0290 RBUF4 Receive Buffer for Serializer 4 0x0204 0294 RBUF5 Receive Buffer for Serializer 5 0x0204 0298 RBUF6 Receive Buffer for Serializer 6 0x0204 029C RBUF7 Receive Buffer for Serializer 7 0x0204 02A0 RBUF8 Receive Buffer for Serializer 8 0x0204 02A4 RBUF9 Receive Buffer for Serializer 9 0x0204 02A8-0x0204 3FFF - Reserved Table 6-73. McASP Data Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS (Used when RSEL or XSEL bits = 0 McASP receive buffers or McASP transmit 0204 4000 - 0204 43FF RBUF/XBUF [these bits are located in the RFMT or buffers via the Peripheral Data Bus. XFMT registers, respectively].) 6.18.1.3 McASP Electrical Data/Timing 6.18.1.3.1 Multichannel Audio Serial Port (McASP) Timing Table 6-74. Timing Requirements for McASP (see Figure 6-49 and Figure 6-50)(1) 720, 800, 900, 1100 NO. UNIT MIN MAX 1 tc(AHCKRX) Cycle time, AHCLKR/X 20 ns 2 tw(AHCKRX) Pulse duration, AHCLKR/X high or low 10 ns 3 tc(CKRX) Cycle time, ACLKR/X ACLKR/X ext 33 ns 4 tw(CKRX) Pulse duration, ACLKR/X high or low ACLKR/X ext 16.5 ns ACLKR/X int 5 ns 5 tsu(FRX-CKRX) Setup time, AFSR/X input valid before ACLKR/X latches data ACLKR/X ext 5 ns ACLKR/X int 5 ns 6 th(CKRX-FRX) Hold time, AFSR/X input valid after ACLKR/X latches data ACLKR/X ext 12.08 ns ACLKR/X int 5 ns 7 tsu(AXR-CKRX) Setup time, AXR input valid before ACLKR/X latches data ACLKR/X ext 5 ns ACLKR/X int 5 ns 8 th(CKRX-AXR) Hold time, AXR input valid after ACLKR/X latches data ACLKR/X ext 7.35 ns (1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 Copyright © 2010–2009, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 151 Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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