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TMS320DM647 Datasheet(PDF) 164 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 164 Page - Texas Instruments |
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164 / 181 page  TMS320DM647 TMS320DM648 SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009 www.ti.com Table 6-81. Ethernet Subsystem Timing Requirements (continued) PARAMETER(1) MIN NOM MAX UNITS t02 REFCLKP/N duty cycle 40 60 % t03 REFCLKP/N rise/fall 700 ps t04 PLL Clock Period, x n Mode t01 / n ns t05 PLL power up 1 + 200 * C ms REFCLKP/N Jitter and PLL Loop Bandwidth Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance thereby impairing system performance. A good quality, low jitter reference clock is necessary to achieve compliance with most if not all physical layer standards (see Table 6-82). Table 6-82. REFCLKP/N Jitter Requirements for Standards Compliance Standard Line Rate (Gbps) Total REFCLKP/N Jitter (within PLL bandwidth) Gigabit Ethernet 1.25 50 ps pk-pk 164 Peripheral Information and Electrical Specifications Copyright © 2010–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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