11-89
RF2908
Rev C1 010904
11
Pin
Function
Description
Interface Schematic
1MOUT Q-
The complementary quadrature phase signal output from the front-end
mixer. See pin 2.
2MOUT Q+
The quadrature phase signal output from the front-end mixer.
3MIX VCC
Supply voltage for the front-end quadrature mixers.
4
MIX GND
Ground connection for the front-end quadrature mixers.
5LNA GND
Ground connection for the low noise amplifier (LNA).
6LNA IN
Input to the attenuator and LNA.
7SW GND
Ground connection for the input attenuator.
8LNA VCC
Supply voltage for the LNA.
9
SW GND2
Ground connection for the input attenuator.
10
ATTN
Input attenuator control point. When connected “high”, the attenuator
adds 20dB of series attenuation. When connected “low”, the attenuator
adds 0dB of series attenuation.
11
MOUT I+
The in-phase signal output from the front-end mixer.
12
MOUT I-
The complementary in-phase signal output from the front-end mixer.
See pin 12.
13
IN I+
Input for the in-phase IF channel.
14
IN I-
Complementary input for the in-phase IF channel.
15
GND2
Ground for VCC2.
16
DCFB I
DC feedback capacitor for in-phase channel.
17
VCC2
Power supply for VGA amplifier 3, differential to single-ended converter,
and post filter.
18
GND3
Ground for VCC3.
19
IF OUT I
Analog signal IF output for in-phase channel.
20
VCC3
Power supply for data amplifier.
21
I DATA
Logic-level data output for the in-phase channel. This is a digital output
signal obtained from the output of a Schmitt trigger.
22
RSSI I
Received signal strength indicator for the in-phase channel.
23
OSC B
Base connection point for external reference crystal. The reference
crystal is connected between this pin and ground.
24
OSC E
Emitter connection point for external reference crystal. Feedback
capacitors are connected between this pin and ground.
25
LE
Latches data entered into the serial port. Data is clocked into the latch
on the rising edge of LE. See table and timing diagram.
26
PLL CLK
PLL shift register clock. The rising edges of this clocking signal load in
the serial data present at the PLL DATA input pin into the internal latch.
See table and timing diagram.
27
PLL DATA
Input data for loading the counters. Clocked, serial data at this port is
presented to the shift register, then to the latch, and finally to the
counter. Each clock transition sends a single bit to the on-board 7-bit
shift register. The MSB is loaded first. See table and timing diagram.
28
PLL GND
Ground connection for the PLL.
29
PLLD VCC
Supply voltage for the PLL.
30
LO OUT B
Complementary local oscillator output. See pin 33.
31
RESNTR+
This port is used to supply DC voltage to the VCO as well as tune the
center frequency of the VCO.
32
RESNTR-
This is the complementary port to pin 31. Refer to pin 31.
33
LO OUT
Local oscillator output.
34
DO
Connection point for the loop filter.
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