SST49LF004B datasheet(13/36 Pages) SST

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EOL Data Sheet

4 Mbit Firmware Hub

SST49LF004B

S71307-03-EOL

12/07

Firmware Memory Write Cycle

FIGURE 5: FIRMWARE MEMORY WRITE CYCLE WAVEFORM

TABLE

5: FIRMWARE MEMORY WRITE CYCLE

Clock

Cycle

Field

Name

Field Contents

LAD[3:0]1

1. Field contents are valid on the rising edge of the present clock cycle.

LAD[3:0]

Direction

Comments

START

1110

LFRAME# must be active (low) for the device to

respond. Only the last field latched before LFRAME#

transitions high will be recognized. The START field

contents (1110b) indicate a Firmware Memory Write

cycle.

IDSEL

0000 to 1111

Indicates which

SST49LF004B device should

respond. If the IDSEL (ID select) field matches the

value of ID[3:0], the device will respond to the mem-

ory cycle.

3-9

MADDR

YYYY

These seven clock cycles make up the 28-bit memory

address. YYYY is one nibble of the entire address.

Addresses are transferred most-significant nibble first.

MSIZE

0000 (1 Byte)

The MSIZE field indicates how many bytes will be

transferred during multi-byte operations. The device

only supports single-byte writes. MSIZE=0000b

DATA

ZZZZ

ZZZZ is the least-significant nibble of the data byte.

DATA

ZZZZ

ZZZZ is the most-significant nibble of the data byte.

TAR0

1111

IN then Float

In this clock cycle, the host drives the bus to all '1's and

then floats the bus prior to the next clock cycle. This is

the first part of the bus “turnaround cycle.”

TAR1

1111 (float)

Float then OUT

The

SST49LF004B takes control of the bus during this

cycle.

RSYNC

0000

OUT

During this clock cycle, the device generates a “ready

sync” (RSYNC) indicating that the device has received

the input data.

TAR0

1111

OUT then Float

In this clock cycle, the

SST49LF004B drives the bus to

all '1's and then floats the bus prior to the next clock

cycle. This is the first part of the bus “turnaround cycle.”

TAR1

1111 (float)

Float then IN

The host resumes control of the bus during this cycle.

T5.0 1307

1307 F04.0

LFRAME#

LAD[3:0]

1110b

0000b

A[23:20] A[19:16]

A[3:0]

A[7:4]

A[11:8]

A[15:12]

MADDR

Start

IDSEL

MSIZE

LCLK

A[27:24]

0000b

RSYNC

TAR1

TAR0

TAR

DATA

D[7:4]

Tri-State

D[3:0]

0000b

1111b

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