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PIC18F23K22-E/ML Datasheet(PDF) 217 Page - Microchip Technology |
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PIC18F23K22-E/ML Datasheet(HTML) 217 Page - Microchip Technology |
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217 / 496 page  2010 Microchip Technology Inc. Preliminary DS41412C-page 217 PIC18(L)F2X/4XK22 15.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSPx clock is much faster than the system clock. In Slave mode, when MSSPx interrupts are enabled, after the master completes sending data, an MSSPx interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSPx interrupts should be disabled. In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/ reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSPx interrupt flag bit will be set and if enabled, will wake the device. TABLE 15-1: REGISTERS ASSOCIATED WITH SPI OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 152 ANSELB — — ANSB5 ANSB4 ANSB3(1) ANSB2(1) ANSB1(1) ANSB0(1) 153 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 153 ANSELD ANSD7 ANSD6 ANSD5 ANSD4(2) ANSD3(2) ANSD2 ANSD1(2) ANSD0(2) 153 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 115 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 127 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 129 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 123 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 125 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 118 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 120 PMD1 MSSP2MD MSSP1MD — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD 57 SSP1BUF SSP1 Receive Buffer/Transmit Register — SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 256 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 259 SSP1STAT SMP CKE D/A P S R/W UA BF 255 SSP2BUF SSP2 Receive Buffer/Transmit Register — SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 256 SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 259 SSP2STAT SMP CKE D/A P S R/W UA BF 255 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 154 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3(1) TRISB2(1) TRISB1(1) TRISB0(1) 154 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 154 TRISD TRISD7 TRISD6 TRISD5 TRISD4(2) TRISD3(2) TRISD2 TRISD1(2) TRISD0(2) 154 Legend: Shaded bits are not used by the MSSPx in SPI mode. Note 1: PIC18(L)F2XK22 devices. 2: PIC18(L)F4XK22 devices. |
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