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PIC18F23K22-E/ML Datasheet(PDF) 290 Page - Microchip Technology |
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PIC18F23K22-E/ML Datasheet(HTML) 290 Page - Microchip Technology |
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290 / 496 page  PIC18(L)F2X/4XK22 DS41412C-page 290 Preliminary 2010 Microchip Technology Inc. 16.4.2.3 EUSART Synchronous Slave Reception The operation of the Synchronous Master and Slave modes is identical (Section 16.4.1.6 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don't care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREGx register. If the RCxIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE/GIEH bit is also set, the program will branch to the interrupt vector. 16.4.2.4 Synchronous Slave Reception Set- up: 1. Set the SYNC and SPEN bits and clear the CSRC bit. 2. Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’. 3. If using interrupts, ensure that the GIE/GIEH and PEIE/GIEL bits of the INTCON register are set and set the RCxIE bit. 4. If 9-bit reception is desired, set the RX9 bit. 5. Set the CREN bit to enable reception. 6. The RCxIF bit will be set when reception is complete. An interrupt will be generated if the RCxIE bit was set. 7. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTAx register. 8. Retrieve the 8 Least Significant bits from the receive FIFO by reading the RCREGx register. 9. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTAx register or by clearing the SPEN bit which resets the EUSART. TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 274 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 274 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 115 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 127 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 129 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 123 PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 125 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 118 PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 120 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD 56 RCREG1 EUSART1 Receive Register — RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 273 RCREG2 EUSART2 Receive Register — RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 273 SPBRG1 EUSART1 Baud Rate Generator, Low Byte — SPBRGH1 EUSART1 Baud Rate Generator, High Byte — SPBRG2 EUSART2 Baud Rate Generator, Low Byte — SPBRGH2 EUSART2 Baud Rate Generator, High Byte — TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 272 TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 272 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception. |
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