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PIC18F23K22-E/ML Datasheet(PDF) 293 Page - Microchip Technology

Part # PIC18F23K22-E/ML
Description  28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology
PDF  496 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F23K22-E/ML Datasheet(HTML) 293 Page - Microchip Technology

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 2010 Microchip Technology Inc.
Preliminary
DS41412C-page 293
PIC18(L)F2X/4XK22
17.1.5
CONVERSION CLOCK
The source of the conversion clock is software
selectable via the ADCS bits of the ADCON2 register.
There are seven possible clock options:
•FOSC/2
•FOSC/4
•FOSC/8
•FOSC/16
•FOSC/32
•FOSC/64
•FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11 TAD periods
as shown in Figure 17-3.
For correct conversion, the appropriate TAD specification
must be met. See A/D conversion requirements in
Table 27-24 for more information. Table gives examples
of appropriate ADC clock selections.
17.1.6
INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
Conversion. The ADC interrupt enable is the ADIE bit
in the PIE1 register and the interrupt priority is the ADIP
bit in the IPR1 register. The ADC interrupt flag is the
ADIF bit in the PIR1 register. The ADIF bit must be
cleared by software.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine.
Note:
Unless using the FRC, any changes in the
system clock frequency will change the
ADC
clock
frequency,
which
may
adversely affect the ADC result.
Note:
The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
TABLE 17-1:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC Clock Source
ADCS<2:0>
64 MHz
16 MHz
4 MHz
1 MHz
FOSC/2
000
31.25 ns(2)
125 ns(2)
500 ns(2)
2.0
s
FOSC/4
100
62.5 ns(2)
250 ns(2)
1.0
s
4.0
s(3)
FOSC/8
001
400 ns(2)
500 ns(2)
2.0
s
8.0
s(3)
FOSC/16
101
250 ns(2)
1.0
s
4.0
s(3)
16.0
s(3)
FOSC/32
010
500 ns(2)
2.0
s
8.0
s(3)
32.0
s(3)
FOSC/64
110
1.0
s
4.0
s(3)
16.0
s(3)
64.0
s(3)
FRC
x11
1-4
s(1,4)
1-4
s(1,4)
1-4
s(1,4)
1-4
s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1:
The FRC source has a typical TAD time of 1.7
s.
2:
These values violate the minimum required TAD time.
3:
For faster conversion times, the selection of another clock source is recommended.
4:
When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.



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