PIC18F23K22-ESLASHML datasheet(296/496 Pages) MICROCHIP

296 / 496 page

PIC18(L)F2X/4XK22

DS41412C-page 296

Preliminary

 2010 Microchip Technology Inc.

17.2.2

COMPLETION OF A CONVERSION

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF flag bit

• Update the ADRESH:ADRESL registers with new

conversion result

17.2.3

DISCHARGE

The discharge phase is used to initialize the value of

the capacitor array. The array is discharged after every

sample. This feature helps to optimize the unity-gain

amplifier, as the circuit always needs to charge the

capacitor array, rather than charge/discharge based on

previous measure values.

17.2.4

TERMINATING A CONVERSION

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared by software. The

ADRESH:ADRESL registers will not be updated with

the partially complete Analog-to-Digital conversion

sample. Instead, the ADRESH:ADRESL register pair

will retain the value of the previous conversion.

17.2.5

DELAY BETWEEN CONVERSIONS

After the A/D conversion is completed or aborted, a

2TAD wait is required before the next acquisition can

be started. After this wait, the currently selected

channel is reconnected to the charge holding capacitor

commencing the next acquisition.

17.2.6

ADC OPERATION IN POWER-

MANAGED MODES

The selection of the automatic acquisition time and A/D

conversion clock is determined in part by the clock

source and frequency while in a power-managed mode.

If the A/D is expected to operate while the device is in

a power-managed mode, the ACQT<2:0> and

ADCS<2:0> bits in ADCON2 should be updated in

accordance with the clock source to be used in that

mode. After entering the mode, an A/D acquisition or

conversion may be started. Once started, the device

should continue to be clocked by the same clock

source until the conversion has been completed.

If desired, the device may be placed into the

corresponding Idle mode during the conversion. If the

device clock frequency is less than 1 MHz, the A/D FRC

clock source should be selected.

17.2.7

ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC waits one additional instruction before starting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

When the ADC clock source is something other than

FRC, a SLEEP instruction causes the present

conversion to be aborted and the ADC module is

turned off, although the ADON bit remains set.

17.2.8

SPECIAL EVENT TRIGGER

Two Special Event Triggers are available to start an A/D

conversion: CTMU and CCP5. The Special Event

Trigger source is selected using the TRIGSEL bit in

ADCON1.

When TRIGSEL = 0, the CCP5 module is selected as

the Special Event Trigger source. To enable the Special

Event Trigger in the CCP module, set CCP5M<3:0> =

1011, in the CCP5CON register.

When TRIGSEL = 1, the CTMU module is selected.

The CTMU module requires that the CTTRIG bit in

CTMUCONH is set to enable the Special Event Trigger.

In addition to TRIGSEL bit, the following steps are

required to start an A/D conversion:

• The A/D module must be enabled (ADON = 1)

• The appropriate analog input channel selected

• The minimum acquisition period set one of these

ways:

- Timing provided by the user

- Selection made of an appropriate TACQ time

With these conditions met, the trigger sets the GO/DONE

bit and the A/D acquisition starts.

If the A/D module is not enabled (ADON = 0), the

module ignores the Special Event Trigger.

17.2.9

PERIPHERAL MODULE DISABLE

When a peripheral module is not used or inactive, the

module can be disabled by setting the Module Disable

bit in the PMD registers. This will reduce power

consumption to an absolute minimum. Setting the PMD

bits holds the module in Reset and disconnects the

module’s clock source. The Module Disable bit for the

ADC module is ADCMD in the PMD2 Register. See

Section 3.0 “Power-Managed Modes” for more

information.

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

PIC18F23K22-E/ML Datasheet(PDF) 296 Page - Microchip Technology

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