PIC18F23K22-ESLASHML datasheet(328/496 Pages) MICROCHIP

328 / 496 page

PIC18(L)F2X/4XK22

DS41412C-page 328

Preliminary

 2010 Microchip Technology Inc.

19.6

Creating a Delay with the CTMU

Module

A unique feature on board the CTMU module is its

ability to generate system clock independent output

pulses based on an external capacitor value. This is

accomplished using the internal comparator voltage

reference module, Comparator 2 input pin and an

external capacitor. The pulse is output onto the CTPLS

pin. To enable this mode, set the TGEN bit.

See Figure 19-4 for an example circuit. CPULSE is

chosen by the user to determine the output pulse width

on CTPLS. The pulse width is calculated by

T =(CPULSE/I)*V, where I is known from the current

source measurement step (Section 19.3.1 “Current

Source Calibration”) and V is the internal reference

voltage (CVREF).

An example use of this feature is for interfacing with

variable capacitive-based sensors, such as a humidity

sensor. As the humidity varies, the pulse width output

on CTPLS will vary. The CTPLS output pin can be con-

nected to an input capture pin and the varying pulse

width is measured to determine the humidity in the

application.

Follow these steps to use this feature:

Initialize Comparator 2.

Initialize the comparator voltage reference.

Initialize the CTMU and enable time delay

generation by setting the TGEN bit.

Set EDG1STAT.

When CPULSE charges to the value of the voltage

reference trip point, an output pulse is generated

on CTPLS.

FIGURE 19-4:

TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE

DELAY GENERATION

19.7

Operation During Sleep/Idle

Modes

19.7.1

SLEEP MODE AND DEEP SLEEP

MODES

When the device enters any Sleep mode, the CTMU

module current source is always disabled. If the CTMU

is performing an operation that depends on the current

source when Sleep mode is invoked, the operation may

not terminate correctly. Capacitance and time

measurements may return erroneous values.

19.7.2

IDLE MODE

The behavior of the CTMU in Idle mode is determined

by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL

is cleared, the module will continue to operate in Idle

mode. If CTMUSIDL is set, the module’s current source

is disabled when the device enters Idle mode. If the

module is performing an operation when Idle mode is

invoked, in this case, the results will be similar to those

with Sleep mode.

19.8

CTMU Peripheral Module Disable

(PMD)

When this peripheral is not used, the Peripheral

Module Disable bit can be set to disconnect all clock

sources to the module, reducing power consumption to

an absolute minimum. See Section 3.6 “Selective

Peripheral Module Control”.

CVREF

CTPLS

PIC18(L)FXXK22 Device

Current Source

Comparator

CTMU

CTED1

C12IN1-

CPULSE

EDG1

PIC18F23K22-E/ML Datasheet(PDF) 328 Page - Microchip Technology

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