PIC18F23K22-ESLASHML datasheet(378/496 Pages) MICROCHIP

378 / 496 page

PIC18(L)F2X/4XK22

DS41412C-page 378

Preliminary

 2010 Microchip Technology Inc.

BNOV

Branch if Not Overflow

Syntax:

BNOV

Operands:

-128

 n  127

Operation:

if OVERFLOW bit is ‘0’

(PC) + 2 + 2n

 PC

Status Affected:

None

Encoding:

1110

0101

nnnn

Description:

If the OVERFLOW bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Decode

Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

‘n’

Process

Data

operation

Example:

HERE

BNOV Jump

Before Instruction

address (HERE)

After Instruction

If OVERFLOW =

address (Jump)

If OVERFLOW =

address (HERE + 2)

BNZ

Branch if Not Zero

Syntax:

BNZ

Operands:

-128

 n  127

Operation:

if ZERO bit is ‘0’

(PC) + 2 + 2n

 PC

Status Affected:

None

Encoding:

1110

0001

nnnn

Description:

If the ZERO bit is ‘0’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Decode

Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

‘n’

Process

Data

operation

Example:

HERE

BNZ

Jump

Before Instruction

address (HERE)

After Instruction

If ZERO

address (Jump)

If ZERO

address (HERE + 2)

PIC18F23K22-E/ML Datasheet(PDF) 378 Page - Microchip Technology

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