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PIC18F23K22-E/ML Datasheet(PDF) 381 Page - Microchip Technology |
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PIC18F23K22-E/ML Datasheet(HTML) 381 Page - Microchip Technology |
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381 / 496 page ![]() 2010 Microchip Technology Inc. Preliminary DS41412C-page 381 PIC18(L)F2X/4XK22 BTG Bit Toggle f Syntax: BTG f, b {,a} Operands: 0 f 255 0 b < 7 a [0,1] Operation: (f<b>) f<b> Status Affected: None Encoding: 0111 bbba ffff ffff Description: Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ Process Data Write register ‘f’ Example: BTG PORTC, 4, 0 Before Instruction: PORTC = 0111 0101 [75h] After Instruction: PORTC = 0110 0101 [65h] BOV Branch if Overflow Syntax: BOV n Operands: -128 n 127 Operation: if OVERFLOW bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None Encoding: 1110 0100 nnnn nnnn Description: If the OVERFLOW bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data No operation Example: HERE BOV Jump Before Instruction PC = address (HERE) After Instruction If OVERFLOW = 1; PC = address (Jump) If OVERFLOW = 0; PC = address (HERE + 2) |
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