PIC18F23K22-ESLASHML datasheet(384/496 Pages) MICROCHIP

384 / 496 page

PIC18(L)F2X/4XK22

DS41412C-page 384

Preliminary

 2010 Microchip Technology Inc.

COMF

Complement f

Syntax:

COMF

f {,d {,a}}

Operands:

 f  255

 [0,1]

Operation:

(f)

 dest

Status Affected:

N, Z

Encoding:

0001

11da

ffff

Description:

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example:

COMF

REG, 0, 0

Before Instruction

REG

13h

After Instruction

REG

13h

ECh

CPFSEQ

Compare f with W, skip if f = W

Syntax:

CPFSEQ

f {,a}

Operands:

 f  255

 [0,1]

Operation:

(f) – (W),

skip if (f) = (W)

(unsigned comparison)

Status Affected:

None

Encoding:

0110

001a

ffff

Description:

Compares the contents of data memory

location ‘f’ to the contents of W by

performing an unsigned subtraction.

If ‘f’ = W, then the fetched instruction is

discarded and a NOP is executed

instead, making this a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

95 (5Fh). See

Section 25.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

operation

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE

CPFSEQ REG, 0

NEQUAL

EQUAL

Before Instruction

PC Address

HERE

REG

After Instruction

If REG

Address (EQUAL)

If REG



Address (NEQUAL)

PIC18F23K22-E/ML Datasheet(PDF) 384 Page - Microchip Technology

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