PIC18F23K22-ESLASHML datasheet(174/496 Pages) MICROCHIP

174 / 496 page

PIC18(L)F2X/4XK22

DS41412C-page 174

Preliminary

 2010 Microchip Technology Inc.

13.1

Timer2/4/6 Operation

The clock input to the Timer2/4/6 module is the system

instruction clock (FOSC/4).

TMRx increments from 00h on each clock edge.

A 4-bit counter/prescaler on the clock input allows direct

input, divide-by-4 and divide-by-16 prescale options.

These options are selected by the prescaler control bits,

TxCKPS<1:0> of the TxCON register. The value of

TMRx is compared to that of the Period register, PRx, on

each clock cycle. When the two values match, the

comparator generates a match signal as the timer

output. This signal also resets the value of TMRx to 00h

the

cycle

and

drives

the

output

counter/postscaler (see Section 13.2 “Timer2/4/6

Interrupt”).

The TMRx and PRx registers are both directly readable

and writable. The TMRx register is cleared on any

device Reset, whereas the PRx register initializes to

FFh. Both the prescaler and postscaler counters are

cleared on the following events:

• a write to the TMRx register

• a write to the TxCON register

• Power-on Reset (POR)

• Brown-out Reset (BOR)

•MCLR Reset

• Watchdog Timer (WDT) Reset

• Stack Overflow Reset

• Stack Underflow Reset

• RESET Instruction

13.2

Timer2/4/6 Interrupt

Timer2/4/6 can also generate an optional device

interrupt. The Timer2/4/6 output signal (TMRx-to-PRx

match)

provides

the

input

for

the

4-bit

counter/postscaler. This counter generates the TMRx

match interrupt flag which is latched in TMRxIF of the

PIR1/PIR5 registers. The interrupt is enabled by setting

the TMRx Match Interrupt Enable bit, TMRxIE of the

PIE1/PIE5 registers. Interrupt Priority is selected with

the TMRxIP bit in the IPR1/IPR5 registers.

A range of 16 postscale options (from 1:1 through 1:16

inclusive) can be selected with the postscaler control

bits, TxOUTPS<3:0>, of the TxCON register.

13.3

Timer2/4/6 Output

The unscaled output of TMRx is available primarily to

the CCP modules, where it is used as a time base for

operations in PWM mode. The timer to be used with a

specific

CCP

module

selected

using

the

CxTSEL<1:0> bits in the CCPTMRS0 and CCPTMRS1

registers.

Timer2 can be optionally used as the shift clock source

for the MSSPx modules operating in SPI mode by

setting SSPM<3:0> = 0011 in the SSPxCON1 register.

Additional information is provided in Section 15.0

“Master Synchronous Serial Port (MSSP1 and

MSSP2) Module”.

13.4

Timer2/4/6 Operation During Sleep

The Timer2/4/6 timers cannot be operated while the

processor is in Sleep mode. The contents of the TMRx

and PRx registers will remain unchanged while the

processor is in Sleep mode.

13.5

Peripheral Module Disable

When a peripheral module is not used or inactive, the

module can be disabled by setting the Module Disable

bit in the PMD registers. This will reduce power con-

sumption to an absolute minimum. Setting the PMD

bits holds the module in Reset and disconnects the

module’s clock source. The Module Disable bits for

Timer2 (TMR2MD), Timer4 (TMR4MD) and Timer6

(TMR6MD) are in the PMD0 Register. See Section 3.0

“Power-Managed Modes” for more information.

Note:

TMRx is not cleared when TxCON is written.

PIC18F23K22-E/ML Datasheet(PDF) 174 Page - Microchip Technology

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