MCP14E3 datasheet(11/26 Pages) MICROCHIP

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DS22062B-page 11

MCP14E3/MCP14E4/MCP14E5

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

3.1

Control Inputs A and B

The MOSFET driver inputs are a high-impedance TTL/

CMOS compatible input. The inputs also have hystere-

sis between the high and low input levels, allowing

them to be driven from slow rising and falling signals

and to provide noise immunity.

3.2

Outputs A and B

Outputs A and B are CMOS push-pull outputs that are

capable of sourcing and sinking 4.0A of peak current

(VDD = 18V). The low output impedance ensures the

gate of the MOSFET will stay in the intended state even

during large transients. These outputs also have a

reverse latch-up rating of 1.5A.

3.3

Supply Input (VDD)

VDD is the bias supply input for the MOSFET driver and

has a voltage range of 4.5V to 18V. This input must be

decoupled to ground with a local ceramic capacitor.

This bypass capacitor provides a localized low-imped-

ance path for the peak currents that are to be provided

to the load.

3.4

Ground (GND)

Ground is the device return pin. The ground pin(s)

should have a low impedance connection to the bias

supply source return. High peak currents will flow out

the ground pin(s) when the capacitive load is being

discharged.

3.5

Enable A (ENB_A)

The ENB_A pin is the enable control for Output A. This

enable pin is internally pulled up to VDD for active high

operation and can be left floating for standard

operation. When the ENB_A pin is pulled below the

enable pin Low Level Input Voltage (VEN_L), Output A

will be in the off state regardless of the input pin state.

3.6

Enable B (ENB_B)

The ENB_B pin is the enable control for Output B. This

enable pin is internally pulled up to VDD for active high

operation and can be left floating for standard

operation. When the ENB_B pin is pulled below the

enable pin Low-Level Input Voltage (VEN_L), Output B

will be in the off state regardless of the input pin state.

3.7

DFN Exposed Pad

The exposed metal pad of the DFN package is not

internally connected to any potential. Therefore, this

pad can be connected to a ground plane or other

copper plane on a printed circuit board to aid in heat

removal from the package.

TABLE 3-1:

PIN FUNCTION TABLE

8-Pin

PDIP, SOIC

8-Pin

6x5 DFN

Symbol

Description

ENB_A

Output A Enable

IN A

Input A

GND

Ground

IN B

Input B

OUT B

Output B

VDD

Supply Input

OUT A

Output A

ENB_B

Output B Enable

—

PAD

Exposed Metal Pad

Note:

Duplicate pins must be connected for proper operation.

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