©2009 CADEKA Microcircuits LLC

www.cadeka.com

24

Data Sheet

The ADC channels have 13 bits of resolution. There are two options for the serial LVDS outputs, 12 bits or 14 bits, se-

lected by setting

lvds_num_bits to '0' or '1', respectively. In 12-bit mode, the LSB bit from the ADCs are removed in the

output stream. In 14-bit mode, a '0' is added in the LSB position. Power down mode must be activated after or during

a change in the number of output bits.

To ease timing in the receiver when using multiple ADC chips, the CDK8307 has the option to adjust the timing of the

output data and the frame clock. The propagation delay with respect to the ADC input clock can be moved one LVDS

clock cycle forward or backward, by using

lvds_advance and lvds_delay, respectively. See figure 8 for details. Note that

LCLK is not affected by

lvds_delay or lvds_advance settings.

Figure 8: LVDS Output Timing Adjustment

Table 15. Full Scale Control

Name

Description

Default

D

1

5

D

1

4

D

1

3

D

1

2

D

1

1

D

1

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Address

In Hex

fs_cntrl<5:0>

Fine adjust ADC full scale range

0% change

X X X X X X

55

The full-scale voltage range of CDK8307 can be adjusted using an internal 6-bit DAC controlled by the

fs_cntrl register.

Changing the value in the register by one step, adjusts the full-scale range approximately 0.3%. This leads to a maximum

range of ±10% adjustment. Table 16 shows how the register settings correspond to the full-scale range. Note that the

values for full-scale range adjustment are approximate. The DAC is, however, guaranteed to be monotonous.

The full-scale control and the programmable gain features differ in two major ways:

1. The full-scale control feature controls the full-scale voltage range in an analog fashion, whereas the programmable

gain is a digital feature.

2. The programmable gain feature has much coarser gain steps and larger range than the full-scale control.

FCLKP

FCLKN

FCLKP

FCLKN

LCLKP

default:

lvds_delay = ‘1’:

lvds_advance = ‘1’:

*LVDS output timing adjustment

LCLKN

Dxx<1:0>

FCLKP

FCLKN

Dxx<1:0>

Dxx<1:0>

D3

N-1

D4

N-1

D5

N-1

D6

N-1

D7

N-1

D8

N-1

D9

N-1

D10

N-1

D11

N-1

D0

N

D1

N

D2

N

D3

N

D4

N

D5

N

D6

N

D7

N

D8

N

D9

N

D2

N-1

D3

N-1

D4

N-1

D5

N-1

D6

N-1

D7

N-1

D8

N-1

D9

N-1

D10

N-1

D11

N-1

D0

N

D1

N

D2

N

D3

N

D4

N

D5

N

D6

N

D7

N

D8

N

D4

N-1

D5

N-1

D6

N-1

D7

N-1

D8

N-1

D9

N-1

D10

N-1

D11

N-1

D0

N

D1

N

D2

N

D3

N

D4

N

D5

N

D6

N

D7

N

D8

N

D9

N

D10

N