©2009 CADEKA Microcircuits LLC

www.cadeka.com

14

Data Sheet

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Logic Inputs (CMOS)

High Level Input Voltage

2

V

V

Low Level Input Voltage

0

0.8

V

0

V

High Level Input Leakage Current

±10

µA

Low Level Input Leakage Current

±10

µA

Input Capacitance

3

pF

Data Outputs (LVDS)

Compliance

LVDS

Differential Output Voltage

350

mV

Output Common Mode Voltage

1.2

V

Output Coding

Default/Optional

Offset Binary/2‘s Complement

Timing Characteristics

Aperture Delay

0.8

ns

Aperture Jitter

<0.5

ps

Start up Time from Power Down

Start up time from Power Down to Active

Mode. References have reached 99% of final

value. (See section Clock Frequency)

260

992

clock

cycles

15

µs

Startup Time from Sleep

Start up time from Sleep Mode to Active Mode

0.5

µs

Out Of Range Recovery Time

1

clk cycles

Pipeline Delay

14

clk cycles

LVDS Output Timing Characterisctics

LCLK to Data Delay Time

Excluding programmable phase shift

250

ps

Clock Propogation Delay

+2.6

+3.5

+4.2

ns

LVDS Bit-Clock Duty-Cycle

45

55

% LCLK

cycle

Frame clock cycle-to-cycle jitter

2.5

% LCLK

cycle

Data Rise- and Fall Time

Calculated from 20% to 80%

0.4

ns

Clock Rise- and Fall Time

Calculated from 20% to 80%

0.4

ns

Note:

(1)

(2) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents

and resulting switching noise at a minimum.