ST10F276Z5 datasheet(176/239 Pages) STMICROELECTRONICS

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ST10F276Z5

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The default XPER selection after Reset is such that CAN1 is enabled, CAN2 is disabled,

XRAM1 (2 Kbyte XRAM) is enabled and XRAM2 (64 Kbyte XRAM) is disabled; all the other

X-Peripherals are disabled after Reset.

after setting of bit XPEN in SYSCON register.

In Emulation mode, all the X-Peripherals are enabled (XPERCON bits are all set). The

bondout chip determines whether or not to redirect an access to external memory or to

XBUS.

Reserved bits of XPERCON register are always written to ‘0’.

Table 87 below summarizes the Segment 8 mapping that depends upon the EA pin status

during reset as well as the SYSCON (bit XPEN) and XPERCON (bits XRAM2EN and

XFLASHEN) registers user programmed values.

Note:

The symbol “x” in the table above stands for “do not care”.

22.10.1

XPERCON and XPEREMU registers

As already mentioned, the XPERCON register must be programmed to enable the single

XBUS modules separately. The XPERCON is a read/write ESFR register; the XPEREMU

Once the XPEN bit of SYSCON register is set and at least one of the X-peripherals (except

memories) is activated, the register XPEREMU must be written with the same content of

XPERCON: This is mandatory in order to allow a correct emulation of the new set of

features introduced on XBUS for the new ST10 generation. The following instructions must

be added inside the initialization routine:

if (SYSCON.XPEN && (XPERCON & 0x07D3))

then { XPEREMU = XPERCON }

Of course, XPEREMU must be programmed after XPERCON and after SYSCON; in this

way the final configuration for X-Peripherals is stored in XPEREMU and used for the

emulation hardware setup.

Note:

The bit meaning is exactly the same as in XPERCON.

Table 87.

Segment 8 address range mapping

XPEN

XRAM2EN

XFLASHEN

Segment 8

External memory

0100

External memory

Reserved

IFlash (B1F1)

XPEREMU (EB7Eh)

XBUS

Reset value xxxxh:

987

65432

---

XMISC

XI2C

XSSC

XASC

XPWM

XFLAS

HEN

XRTC

XRAM2

XRAM1

CAN2

CAN1

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