ST10F276Z5 datasheet(215/239 Pages) STMICROELECTRONICS

215 / 239 page

ST10F276Z5

Electrical characteristics

215/239

Partially tested, guaranteed by design characterization.

The following figures (Figure 57 to Figure 64) present the different configurations of external

memory cycle.

t38

ALE falling edge to

Latched CS

– 4 – tA

6 – tA

– 4 – tA

6 – tA

t39

Latched CS low to

Valid Data In

–

16.5 + tC +

2tA

–

3TCL – 21+ tC +

2tA

t41

Latched CS hold after

RD, WR

2 + tF

–

TCL – 10.5 + tF

–ns

t82

Address setup to

RdCS, WrCS

(with RW-delay)

14 + 2tA

–

2TCL – 11 +

2tA

–ns

t83

Address setup to

RdCS, WrCS

(no RW-delay)

2 + 2tA

–

TCL –10.5 +

2tA

–ns

t46

RdCS to Valid Data In

(with RW-delay)

–4 + tC

–

2TCL – 21 + tC

t47

RdCS to Valid Data In

(no RW-delay)

–

16.5 + tC

–

3TCL – 21 + tC

t48

RdCS, WrCS low time

(with RW-delay)

15.5 + tC

–

2TCL – 9.5 + tC

–ns

t49

RdCS, WrCS low time

(no RW-delay)

28 + tC

–

3TCL – 9.5 + tC

–ns

t50

CC Data valid to WrCS

10 + tC

–

2TCL – 15 + tC

–ns

t51

SR Data hold after RdCS

0–

–

t53

Data float after RdCS

(with RW-delay)

–

16.5 + tF

–

2TCL – 8.5 + tF ns

t68

Data float after RdCS

(no RW-delay)

–4 + tF

–

TCL – 8.5 + tF

t55

Address hold after

RdCS, WrCS

– 8.5 + tF

–

– 8.5 + tF

–ns

t57

CC Data hold after WrCS

2 + tF

–

TCL – 10.5 + tF

–ns

RW-delay and

A refer to the next following bus cycle.

Read data is latched with the same clock edge that triggers the address change and the rising RD edge.

Therefore address changes which occur before the end of RD have no impact on read cycles.

Table 107.

Demultiplexed bus (continued)

Symbol

Parameter

FCPU = 40 MHz

TCL = 12.5 ns

Variable CPU clock

1/2 TCL = 1 to 64 MHz

Min.

Max.

Min.

Max.

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