ST10F276Z5 datasheet(233/239 Pages) STMICROELECTRONICS

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ST10F276Z5

Known limitations

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However, in certain cases, the PWRDN instruction is not ignored, no further instructions are

fetched from external memory, and the CPU is in a quasi-idle state. This problem only

occurs in the following situations:

The instructions following the PWRDN instruction are located in an external memory

and a multiplexed bus configuration with memory tri-state waitstate (bit MTTCx = 0) is

used.

The instruction preceding the PWRDN instruction writes to the external memory or to

an XPeripheral (such as XRAM or CAN) and the instructions following the PWRDN

instruction are located in external memory area. In this case, the problem occurs for all

bus configurations.

Note: The on-chip peripherals, such as the watchdog timer, still operate properly. If the

watchdog timer is not disabled, it resets the device upon an overflow event. However,

interrupts and PEC transfers cannot be processed. Power-down mode is entered if

the NMI signal is asserted low while the device is in this quasi-idle state.

No problem occurs and the device normally enters Power-down mode if the NMI pin is held

low (PWDCFG = 0) or if all Port 2 pins used to exit from Power-down mode are at inactive

level (PWDCFG = 1).

Workaround

To prevent this problem from occurring, the PWRDN instruction must be preceded by

instructions performing write operations to external memory area or to an XPeripheral.

Otherwise, it is recommended to insert a NOP instruction before PWRDN.

When using a multiplexed bus with memory tri-state wait state, the PWRDN instruction must

be executed from internal RAM or XRAM.

24.1.6

Behavior of CAPCOM outputs in COMPARE mode 3

Description

When a CAPCOM channel is configured in compare mode 3, then the related output level

switches to high when the allocated timer, Tx, matches the related CAPCOM register, CCy.

When an overflow occurs on the CAPCOM timer Tx, it is reloaded with TxREL content and

the output pin is cleared. The output pin level does not change if TxREL and CCy have the

same value.

The related CAPCOM output stays low when the CAPCOM channel is configured in

compare mode 3 and TxREL and Tx related timer registers are loaded with the same value

as CCy. This is obtained by executing the following instructions:

MOV TxREL, #CCy value x =0,1,7,8

MOV Tx, #CCy value x = 0,1,7,8

MOV TxxCON, #data or bfldl/bfldh TxxCON , #mask, #data i.e. an

access is made to the T01CON or T78CON register.

ST10F276Z5 Datasheet(PDF) 233 Page - STMicroelectronics