P89LPC9211FDH datasheet(38/75 Pages) NXP

38 / 75 page

P89LPC92X1

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Product data sheet

Rev. 2 — 1 December 2010

38 of 75

NXP Semiconductors

P89LPC9201/9211/922A1/9241/

8-bit microcontroller with 8-bit ADC

7.22.4 Mode 3

11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8

data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is

the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable

and is determined by the Timer 1 overflow rate or the baud rate generator (described in

Section 7.22.5 “Baud rate generator and selection”).

7.22.5 Baud rate generator and selection

The P89LPC9201/9211/922A1/9241/9251 enhanced UART has an independent baud

rate generator. The baud rate is determined by a baud-rate preprogrammed into the

BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works

in a similar manner as Timer 1 but is much more accurate. If the baud rate generator is

used, Timer 1 can be used for other timing functions.

The UART can use either Timer 1 or the baud rate generator output (see Figure 10). Note

that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The

independent baud rate generators use OSCCLK.

7.22.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)

is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is

logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up

when SMOD0 is logic 0.

7.22.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the device

and force the device into ISP mode.

7.22.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be

written to SnBUF while the first character is being transmitted. Double buffering allows

transmission of a string of characters with only one stop bit between any two characters,

as long as the next character is written between the start bit and the stop bit of the

previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is

compatible with the conventional 80C51 UART. If enabled, the UART allows writing to

SBUF while the previous data is being shifted out. Double buffering is only allowed in

Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled

(DBMOD = 0).

Fig 10. Baud rate sources for UART (Modes 1, 3)

baud rate modes 1 and 3

SBRGS = 1

SBRGS = 0

SMOD1 = 0

SMOD1 = 1

timer 1 overflow

(PCLK-based)

baud rate generator

(CCLK-based)

002aaa897

÷2

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