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P89LPC9211FDH Datasheet(PDF) 50 Page - NXP Semiconductors

Part # P89LPC9211FDH
Description  8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB 3 V byte-erasable flash with 8-bit ADC
PDF  75 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

P89LPC9211FDH Datasheet(HTML) 50 Page - NXP Semiconductors

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P89LPC92X1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 1 December 2010
50 of 75
NXP Semiconductors
P89LPC9201/9211/922A1/9241/
8-bit microcontroller with 8-bit ADC
8.7 Boundary limits interrupt
Each of the A/D converters has both a high and low boundary limit register. The user may
select whether an interrupt is generated when the conversion result is within (or equal to)
the high and low boundary limits or when the conversion result is outside the boundary
limits. An interrupt will be generated, if enabled, if the result meets the selected interrupt
criteria. The boundary limit may be disabled by clearing the boundary limit interrupt
enable.
An early detection mechanism exists when the interrupt criteria has been selected to be
outside the boundary limits. In this case, after the four MSBs have been converted, these
four bits are compared with the four MSBs of the boundary high and low registers. If the
four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits)
an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt
criteria, the boundary limits will again be compared after all 8 bits have been converted.
The boundary status register (BNDSTA0) flags the channels which caused a boundary
interrupt.
8.8 DAC output to a port pin with high output impedance
The DAC block of ADC1 can be output to a port pin. In this mode, the AD1DAT3 register is
used to hold the value fed to the DAC. After a value has been written to the DAC (written
to AD1DAT3), the DAC output will appear on the channel 3 pin.
8.9 Clock divider
The ADC requires that its internal clock source be in the range of 320 kHz to 8 MHz to
maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is
provided for this purpose.
8.10 Power-down and Idle mode
In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit
Idle mode when the conversion is completed if the A/D interrupt is enabled. In
Power-down mode or Total Power-down mode, the A/D and temperature sensor do not
function. If temperature sensor or the A/D are enabled, they will consume power. Power
can be reduced by disabling temperature sensor and A/D.



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