MPC8377E datasheet(25/126 Pages) FREESCALE

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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

Figure 7 shows the MII transmit AC timing diagram.

Figure 7. MII Transmit AC Timing Diagram

8.2.1.2

MII Receive AC Timing Specifications

Table 27 provides the MII receive AC timing specifications.

TX_CLK data clock rise (20%–80%)

tMTXR

1.0

—

4.0

TX_CLK data clock fall (80%–20%)

tMTXF

1.0

—

4.0

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII

transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in

general, the clock reference symbol representation is based on two to three letters representing the clock of a particular

functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

Table 27. MII Receive AC Timing Specifications

At recommended operating conditions with LVDD of 3.3 V ± 5%.

Parameter

Symbol1

Min

Typical

Max

Unit

Input low voltage

VIL

——

0.7

Input high voltage

VIH

1.9

—

RX_CLK clock period 10 Mbps

tMRX

—400

—

RX_CLK clock period 100 Mbps

tMRX

—40—

RX_CLK duty cycle

tMRXH/tMRX

—

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

tMRDVKH

10.0

—

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

tMRDXKH

10.0

—

Table 26. MII Transmit AC Timing Specifications (continued)

At recommended operating conditions with LVDD of 3.3 V ± 5%.

Parameter

Symbol1

Min

Typical

Max

Unit

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

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