K40P81M100SF2 datasheet(21/60 Pages) FREESCALE

Part #	K40P81M100SF2

Description	K40 Sub-Family Data Sheet

PDF	60 Pages

Scroll/Zoom	100%

Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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21 / 60 page

Table 11. JTAG electricals (continued)

Symbol

Description

Min.

Max.

Unit

TCLK clock pulse width

• JTAG and CJTAG

• Serial Wire Debug

—

TCLK rise and fall times

—

Boundary scan input data setup time to TCLK rise

—

Boundary scan input data hold time after TCLK rise

—

TCLK low to boundary scan output data valid

—

TCLK low to boundary scan output high-Z

—

TMS, TDI input data setup time to TCLK rise

—

J10

TMS, TDI input data hold time after TCLK rise

—

J11

TCLK low to TDO data valid

—

J12

TCLK low to TDO high-Z

—

J13

TRST assert time

100

—

J14

TRST setup time (negation) to TCLK high

—

TCLK (input)

Figure 5. Test clock input timing

Peripheral operating requirements and behaviors

K40 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.

Freescale Semiconductor, Inc.

Preliminary

K40P81M100SF2 Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc

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