ADL5502ACBZ-P2 datasheet(15/28 Pages) AD

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ADL5502

Rev. A | Page 15 of 28

CIRCUIT DESCRIPTION

The ADL5502 employs two-stage detection. The critical aspect

of this technical approach is the concept of first stripping the

carrier to reveal the envelope and then performing the required

analog computation of rms and peak or any other aspect of the

envelope. An on-chip, 2-pole, passive low-pass filter preserves

the envelope frequencies up to 10 MHz and filters out the carrier.

This carrier filtering ensures that the carrier does not introduce

an error in the peak measurement.

The extracted envelope is further processed in two parallel

channels, one computing the rms value of the envelope and the

other transferring the envelope with appropriate scaling to the

output buffer.

RMS CIRCUIT DESCRIPTION AND FILTERING

The rms processing is done using a proprietary translinear

technique. This method is a mathematically accurate rms

computing approach and allows achieving unprecedented rms

accuracies for complex modulation signals irrespective of the

crest factor of the input signal. An integrating filter capacitor

does the square-domain averaging. The VRMS output can be

expressed as

VRMS

−

∫

Note that A is a scaling parameter that is decided on by the on-chip

resistor ratio, and there are no other scaling parameters involved in

this computation, which means that the rms output is inherently

free from any sources of error due to temperature, supply, and

process variation.

FILTERING

The on-chip rms filtering is sufficient for most common handset

applications, but an external filter capacitor can be connected

if additional filtering is required; however, this increases the

averaging time (see the Selecting the Square-Domain Filter and

Output Low-Pass Filter section). The on-chip rms filter has a

nominal corner frequency of 40 kHz. Any external capacitor

acts on a 1 kΩ resistor to yield a new corner frequency for the

rms filter (see Figure 1).

ENVELOPE PEAK-HOLD CIRCUIT

The envelope signal is processed through a peak-hold circuit,

using the gate of an NMOS device with a charge holding capacitor

connected to ground, driven by a one way charging path. This

low leakage node allows peak-hold times of >1 ms without

practically any drop in voltage. This circuit has the option of either

transferring the envelope in real-time or in the peak-hold mode

by toggling a control logic pin (CNTL). In the peak-hold mode,

the output only is updated when a peak bigger than the previous

biggest peak occurs. The PEAK output can be expressed as

()

[

] 2

max

envelope

PEAK

where:

is the time at which CNTL goes from high to low which is

followed by a time where CNTL stays low.

is the time at which the PEAK measurement is taken, while

CNTL is still low. Here again the only scaling parameter involved is

a Scalar B, which is also decided on by the on-chip resistor ratio.

OUTPUT BUFFERS

A dual buffer takes in internal rms and envelope/peak signals

and gains these up accordingly before these are brought out on

the VRMS and PEAK pins. The output stage of the rms buffer is

a common source PMOS with a resistive load to provide a rail-

to-rail output. However, output stage of the PEAK buffer is an

emitter-follower NPN stage with a resistive load to provide high

speed characteristics for this output. This however limits the

maximum voltage on the PEAK output to about 1.2 V below

supply, resulting in a lower scaling factor for the PEAK signal

path. Such a stage allows fast tracking of a rising transition when a

very narrow peak is to be followed in the 10 MHz signal band-

width. It is highly recommended that capacitive loads greater

than 2 pF are avoided on the PEAK output to realize the full

bandwidth potential of the device.

Both the buffers have 100 Ω on-chip series resistances on the

output. This allows for easy low-pass filtering of the two outputs.

MEASURING THE CREST FACTOR

After proper calibration of the rms and envelope channels, the

ratio of the two outputs gives the crest factor of the signal, when

envelope output is in peak-hold mode (see the Calculation of

Crest Factor (CF) section for more details). The envelope

extraction that precedes rms and peak/envelope measurement is

common to both channels. In addition, the rms and envelope

channels share bias lines and other critical devices that are matched

between the two channels, wherever possible. This ensures that the

relative measurement between the two channels or the crest

factor measurement of the signal is more accurate than the

individual measurements of the rms value and the peak value,

although these measurements in themselves are very accurate

over temperature, supply, and process variations as well.

ADL5502ACBZ-P2 Datasheet(PDF) 15 Page - Analog Devices

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