MPC8360E datasheet(22/108 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor

DDR and DDR2 SDRAM

Table 17 provides the DDR capacitance when GVDD(typ) = 2.5 V.

6.2

DDR and DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.

6.2.1

DDR and DDR2 SDRAM Input AC Timing Specifications

Table 18 provides the input AC timing specifications for the DDR2 SDRAM interface when

GVDD(typ) = 1.8 V.

Table 19 provides the input AC timing specifications for the DDR SDRAM interface when

GVDD(typ) = 2.5 V.

Table 17. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS

CIO

Delta input/output capacitance: DQ, DQS

CDIO

—0.5

Note:

1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.

Table 18. DDR2 SDRAM Input AC Timing Specifications for GVDD(typ) = 1.8 V

At recommended operating conditions with GVDD of 1.8 V ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

VIL

—MVREF – 0.25

—

AC input high voltage

VIH

MVREF + 0.25

—

Table 19. DDR SDRAM Input AC Timing Specifications

At recommended operating conditions with GVDD of 2.5 V ± 5%.

Parameter

Symbol

Min

Max

Unit

Notes

AC input low voltage

VIL

—MVREF – 0.31

—

AC input high voltage

VIH

MVREF + 0.31

—

Note:

1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0

≤ n ≤ 7)

or ECC (MECC[{0...7}] if n = 8).

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