MPC8360E datasheet(63/108 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor

UTOPIA/POS

Figure 46 provides the AC test load for the UTOPIA.

Figure 46. UTOPIA AC Test Load

Figure 47 and Figure 48 represent the AC timing from Table 56. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Figure 47 shows the UTOPIA timing with external clock.

Figure 47. UTOPIA AC Timing (External Clock) Diagram

UTOPIA inputs—Internal clock input setup time

tUIIVKH

6—

—

UTOPIA inputs—External clock input setup time

tUEIVKH

4—

UTOPIA inputs—Internal clock input hold time

tUIIXKH

2.4

—

UTOPIA inputs—External clock input hold time

tUEIXKH

1—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUIKHOX symbolizes the UTOPIA

outputs internal timing (UI) for the time tUTOPIA memory clock reference (K) goes from the high state (H) until outputs (O) are

invalid (X).

3. In rev. 2.0 silicon, due to errata, tUEIVKH minimum is 4.3 ns and tUEIXKH minimum is 1.4 ns under specific conditions. Refer to

Errata QE_UPC3 in

Chip Errata for the MPC8360E, Rev. 1.

Table 60. UTOPIA AC Timing Specifications1 (continued)

Characteristic

Symbol2

Min

Max

Unit

Notes

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

UtopiaCLK (Input)

tUEIXKH

tUEIVKH

tUEKHOV

Input Signals:

UTOPIA

Output Signals:

UTOPIA

tUEKHOX

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