R5F562TADDFH datasheet(85/94 Pages) RENESAS

85 / 94 page

R01DS0096EJ0100 Rev.1.00

Page 85 of 92

Apr 20, 2011

RX62T Group

5. Electrical Characteristics

5.7

ROM (Flash Memory for Code Storage) Characteristics

Note 1. Definition of rewrite/erase cycle:

The rewrite/erase cycle is the number of erasing for each block. When the rewrite/erase cycle is n times (n = 1000), erasing can

be performed n times for each block. For instance, when 256-byte writing is performed 16 times for different addresses in 4-

Kbyte block and then the entire block is erased, the rewrite/erase cycle is counted as one. However, writing to the same address

for several times as one erasing is not enabled (overwriting is prohibited).

Note 2. This indicates the minimum number that guarantees the characteristics after rewriting. (The guaranteed value is in the range

from one to the minimum number.)

Note 3. This indicates the characteristic when rewrite is performed within the specification range including the minimum number.

Table 5.19

ROM (Flash Memory for Code Storage) Characteristics

Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.

Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC

Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Temperature range for the programming/erasure operation:

Ta = -40 to +85°C. Ta is the same under conditions 1 to 3.

Item

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

Programming time

256 bytes

tP256

PCLK = 50 MHz

NPEC  100

4 Kbytes

tP4K

2350ms

16 Kbytes

tP16K

200

256 byte

tP256

2.4

14.4

PCLK = 50 MHz

NPEC > 100

4 Kbytes

tP4K

27.6

16 Kbytes

tP16K

108

240

Erasure time

4 Kbytes

tE4K

2560ms

PCLK = 50 MHz

NPEC  100

16 Kbytes

tE16K

100

240

4 Kbytes

tE4K

3072ms

PCLK = 50 MHz

NPEC > 100

16 Kbytes

tE16K

120

288

Rewrite/erase cycle*1

NPEC

1000*2

--Times

Suspend delay time during writing

tSPD

120

s

Figure 5.24

PCLK = 50 MHz

First suspend delay time during

erasing (in suspend priority mode)

tSESD1

120

s

Second suspend delay time during

erasing (in suspend priority mode)

tSESD2

--1.7

Suspend delay time during erasing

(in erasure priority mode)

tSEED

--1.7

Data hold time*3

tDRP

Year

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