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PIC32MX795F512LT-80I/PF Datasheet(PDF) 198 Page - Microchip Technology |
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PIC32MX795F512LT-80I/PF Datasheet(HTML) 198 Page - Microchip Technology |
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198 / 256 page  PIC32MX5XX/6XX/7XX DS61156G-page 198 © 2009-2011 Microchip Technology Inc. FIGURE 31-4: POWER-ON RESET TIMING CHARACTERISTICS VDD VPOR Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from BOR (VDD < VDDMIN). 2: Includes interval voltage regulator stabilization delay. SY00 Power-up Sequence (Note 2) Internal Voltage Regulator Enabled (TPU) SY10 CPU Starts Fetching Code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR SY00 Power-up Sequence (Note 2) Internal Voltage Regulator Enabled (TPU) (TSYSDLY) CPU Starts Fetching Code (Note 1) (Note 1) Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) (TOST) SY02 (TSYSDLY) SY02 |
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