PIC32MX795F512LT-80ISLASHPF datasheet(62/256 Pages) MICROCHIP

62 / 256 page

TABLE 4-1:

BUS MATRIX REGISTER MAP

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

2000

BMXCON(1)

31:16

—

BMXCHEDMA

—

BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F

15:0

—

—BMXWSDRM

—

BMXARB<2:0>

0041

2010 BMXDKPBA(1)

31:16

—

0000

15:0

BMXDKPBA<15:0>

0000

2020 BMXDUDBA(1)

31:16

—

0000

15:0

BMXDUDBA<15:0>

0000

2030 BMXDUPBA(1)

31:16

—

0000

15:0

BMXDUPBA<15:0>

0000

2040 BMXDRMSZ

31:16

BMXDRMSZ<31:0>

xxxx

15:0

xxxx

2050 BMXPUPBA(1)

31:16

—

BMXPUPBA<19:16>

0000

15:0

BMXPUPBA<15:0>

0000

2060 BMXPFMSZ

31:16

BMXPFMSZ<31:0>

xxxx

15:0

xxxx

2070 BMXBOOTSZ

31:16

BMXBOOTSZ<31:0>

0000

15:0

3000

Legend:

x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.

PIC32MX795F512LT-80I/PF Datasheet(PDF) 62 Page - Microchip Technology

PIC32MX795F512LT-80I/PF Datasheet(HTML) 62 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL