PIC32MX795F512LT-80ISLASHPF datasheet(82/256 Pages) MICROCHIP

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6630 U6RXREG

31:16

—

0000

15:0

—

RX8

Receive Register

0000

6640

U6BRG(1)

31:16

—

0000

15:0

BRG<15:0>

0000

6800 U2MODE(1)

31:16

—

0000

15:0

FRZ

SIDL

IREN

RTSMD

—

UEN<1:0>

WAKE

LPBACK

ABAUD

RXINV

BRGH

PDSEL<1:0>

STSEL

0000

6810

U2STA(1)

31:16

—

ADM_EN

ADDR<7:0>

0000

15:0

UTXISEL<1:0>

UTXINV

URXEN

UTXBRK

UTXEN

UTXBF

TRMT

URXISEL<1:0>

ADDEN

RIDLE

PERR

FERR

OERR

URXDA

0110

6820

U2TXREG

31:16

—

0000

15:0

—

TX8

Transmit Register

0000

6830 U2RXREG

31:16

—

0000

15:0

—

RX8

Receive Register

0000

6840

U2BRG(1)

31:16

—

0000

15:0

BRG<15:0>

0000

6A00 U5MODE(1)

31:16

—

0000

15:0

FRZ

SIDL

IREN

—

WAKE

LPBACK

ABAUD

RXINV

BRGH

PDSEL<1:0>

STSEL

0000

6A10

U5STA(1)

31:16

—

ADM_EN

ADDR<7:0>

0000

15:0

UTXISEL<1:0>

UTXINV

URXEN

UTXBRK

UTXEN

UTXBF

TRMT

URXISEL<1:0>

ADDEN

RIDLE

PERR

FERR

OERR

URXDA

0110

6A20 U5TXREG

31:16

—

0000

15:0

—

TX8

Transmit Register

0000

6A30 U5RXREG

31:16

—

0000

15:0

—

RX8

Receive Register

0000

6A40

U5BRG(1)

31:16

—

0000

15:0

BRG<15:0>

0000

TABLE 4-13:

UART1 THROUGH UART6 REGISTER MAP (CONTINUED)

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

Legend:

x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.

PIC32MX795F512LT-80I/PF Datasheet(PDF) 82 Page - Microchip Technology

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