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PIC32MX795F512LT-80I/PF Datasheet(PDF) 109 Page - Microchip Technology |
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PIC32MX795F512LT-80I/PF Datasheet(HTML) 109 Page - Microchip Technology |
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109 / 256 page ![]() 53B0 U1EP11 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 53C0 U1EP12 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 53D0 U1EP13 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 53E0 U1EP14 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 53F0 U1EP15 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000 TABLE 4-44: USB REGISTER MAP(1) (CONTINUED) Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 2: This register does not have associated SET and INV registers. 3: This register does not have associated CLR, SET and INV registers. 4: Reset value for this bit is undefined. |
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