LPC1850_1109 datasheet(81/142 Pages) NXP

81 / 142 page

LPC1850_30_20_10

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Preliminary data sheet

Rev. 2.2 — 9 September 2011

81 of 142

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

7.18.7 System PLL1

The PLL1 accepts an input clock frequency from an external oscillator in the range of

10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO

operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop

to keep the CCO within its frequency range while the PLL is providing the desired output

frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output

clock. Since the minimum output divider value is 2, it is insured that the PLL output has a

50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be

enabled by software. The program must configure and activate the PLL, wait for the PLL

to lock, and then connect to the PLL as a clock source. The PLL settling time is 100

s.

7.18.8 Reset Generation Unit (RGU)

The RGU allows generation of independent reset signals for individual blocks and

peripherals.

7.18.9 Power control

The LPC1850/30/20/10 feature several independent power domains to control power to

the core and the peripherals (see Figure 11). The RTC and its associated peripherals (the

alarm timer, the CREG block, the OTP controller, the back-up registers, and the event

router) are located in the RTC power-domain which can be powered by a battery supply or

the main regulator. A power selector switch ensures that the RTC block is always powered

on.

LPC1850_1109 Datasheet(PDF) 81 Page - NXP Semiconductors