74LVC1G00GV datasheet(1/17 Pages) PHILIPS

Part #	74LVC1G00GV

Description	Single 2-input NAND gate

PDF	17 Pages

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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1.

General description

The 74LVC1G00 provides the single 2-input NAND function.

Input can be driven from either 3.3 V or 5 V devices. These features allow the use of

these devices in a mixed 3.3 V and 5 V environment.

Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall

time.

This device is fully specified for partial power-down applications using IOFF.

The IOFF circuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

2.

Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 High noise immunity

 Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8-B/JESD36 (2.7 V to 3.6 V)



24 mA output drive (V

CC =3.0 V)

 CMOS low power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Inputs accept voltages up to 5 V

 Multiple package options

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 Specified from

40 Cto+85 C and 40 C to +125 C

74LVC1G00

Single 2-input NAND gate

Rev. 9 — 7 December 2011

Product data sheet

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NXP Semiconductors	74LVC1G00GV	86Kb / 15P	Single 2-input NAND gate 2004 Sep 07
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74LVC1G00GV Datasheet(PDF) 1 Page - NXP Semiconductors

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