74LVC1G00

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© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 9 — 7 December 2011

2 of 17

NXP Semiconductors

74LVC1G00

Single 2-input NAND gate

3.

Ordering information

4.

Marking

[1]

The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5.

Functional diagram

Table 1.

Ordering information

Type number

Package

Temperature range

Name

Description

Version

74LVC1G00GW

40 C to +125 C

TSSOP5

plastic thin shrink small outline package;

5 leads; body width 1.25 mm

SOT353-1

74LVC1G00GV

40 C to +125 C

SC-74A

plastic surface-mounted package; 5 leads

SOT753

74LVC1G00GM

40 C to +125 C

XSON6

plastic extremely thin small outline package;

no leads; 6 terminals; body 1

 1.45  0.5 mm

SOT886

74LVC1G00GF

40 C to +125 C

XSON6

plastic extremely thin small outline package;

no leads; 6 terminals; body 1

 1  0.5 mm

SOT891

74LVC1G00GN

40 C to +125 C

XSON6

extremely thin small outline package; no leads;

6 terminals; body 0.9

 1.0  0.35 mm

SOT1115

74LVC1G00GS

40 C to +125 C

XSON6

extremely thin small outline package; no leads;

6 terminals; body 1.0

 1.0  0.35 mm

SOT1202

Table 2.

Marking codes

Type number

Marking[1]

74LVC1G00GW

VA

74LVC1G00GV

V00

74LVC1G00GM

VA

74LVC1G00GF

VA

74LVC1G00GN

VA

74LVC1G00GS

VA

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram

mna097

B

A

Y

2

1

4

mna098

2

4

&

1

mna099

B

A

Y