HT37A70 datasheet(35/85 Pages) HOLTEK

35 / 85 page

HT37A70/60/50/40/30/20

Rev. 1.00

February 17, 2009

mov a, 01h

; enable timer2 interrupt

mov intch,a

;setup Timer 0 registers

mov a, low (65536-1382)

; setup Timer preload low byte value, interrupt in 1kHz

mov TMR0L,a;

mov a, high (65536-1382)

; setup Timer preload high byte value

mov TMR0H,a;

mov a,080h

; setup Timer 0 control register

mov tmr0c,a

; timer mode and clock source is fOSC/8

® 0.7234ms

set tmr0c.4

; start Timer - note mode bits must be previously setup

mov a, low (256-173)

; setup Timer preload value, interrupt in 2kHz

mov TMR1,a;

mov a,080h

; setup Timer 1control register

mov tmr1c,a

; timer mode and Prescaler output is fOSC/32

® 2.89ms

set tmr1c.4

; start Timer - note mode bits must be previously setup

mov a, low (256-173)

; setup Timer preload value, interrupt in 4kHz

mov TMR2,a;

mov a,080h

; setup Timer2 control register

mov tmr2c,a

; timer mode and Prescaler output is fOSC/16

® 1.447ms

set tmr2c.4

; start Timer - note mode bits must be previously setup

Interrupts

Interrupts are an important part of any microcontroller

system. When an external event or an internal function

such as a Timer/Event Counter 0/1/2 or ERCOCI re-

quire or an ADPCM empty requires microcontroller at-

tention, their corresponding interrupt will enforce a

temporary suspension of the main program allowing the

microcontroller to direct attention to their respective

needs. Each device in this series contains a single ex-

ternal interrupt and two internal interrupts functions. The

external interrupt is controlled by the action of the exter-

nal INT pin, while the internal interrupts are controlled by

the Timer/Event 0/1Counter overflow or ERCOCI re-

quire or the ADPCM empty interrupt.

Interrupt Register

Overall interrupt control, which means interrupt enabling

and request flag setting, is controlled by INTC and

INTCH registers, which are located in Data Memory. By

controlling the appropriate enable bits in this register

each individual interrupt can be enabled or disabled.

Also when an interrupt occurs, the corresponding re-

quest flag will be set by the microcontroller. The global

enable flag if cleared to zero will disable all interrupts.

Interrupt Operation

Timer/Event 0/1/2 Counter overflow, ERCOCI interrupt,

ADPCM empty request or the external interrupt line be-

ing pulled low will all generate an interrupt request by

setting their corresponding request flag, if their appropri-

ate interrupt enable bit is set. When this happens, the

Program Counter, which stores the address of the next

instruction to be executed, will be transferred onto the

stack. The Program Counter will then be loaded with a

new address which will be the value of the correspond-

ing interrupt vector. The microcontroller will then fetch its

next instruction from this interrupt vector. The instruction

at this vector will usually be a JMP statement which will

jump to another section of program which is known as

the interrupt service routine. Here is located the code to

control the appropriate interrupt. The interrupt service

routine must be terminated with a RETI statement,

which retrieves the original Program Counter address

from the stack and allows the microcontroller to continue

with normal execution at the point where the interrupt

occurred.

HT37A70 Datasheet(PDF) 35 Page - Holtek Semiconductor Inc

HT37A70 Datasheet(HTML) 35 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

Datasheet Download

Link URL