R5F10RF8AFP datasheet(50/76 Pages) RENESAS

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RL78/L12

2. ELECTRICAL SPECIFICATIONS (TARGET)

Page 50 of 73

R01DS0157EJ0001 Rev.0.01

2012.02.20

Under development

Preliminary document

Specifications in this document are tentative and subject to change.

Caution

The pins mounted depend on the product.

Refer to 1.3.1

32-pin products to 1.3.5

64-pin

products.

(7) Communication at different potential (2.5 V, 3 V)

(CSI mode) (slave mode, SCKp... external clock input)

(TA =

−40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

20 MHz < fMCK

≤ 24 MHz

12/fMCK

8 MHz < fMCK

≤ 20 MHz

10/fMCK

4 MHz < fMCK

≤ 8 MHz

8/fMCK

4.0 V

≤ EVDD ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V

fMCK

≤ 4 MHz

6/fMCK

20 MHz < fMCK

≤ 24 MHz

16/fMCK

16 MHz < fMCK

≤ 20 MHz

14/fMCK

8 MHz < fMCK

≤ 16 MHz

12/fMCK

4 MHz < fMCK

≤ 8 MHz

8/fMCK

2.7 V

≤ EVDD < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V

fMCK

≤ 4 MHz

6/fMCK

20 MHz < fMCK

≤ 24 MHz

36/fMCK

16 MHz < fMCK

≤ 20 MHz

32/fMCK

8 MHz < fMCK

≤ 16 MHz

26/fMCK

4 MHz < fMCK

≤ 8 MHz

16/fMCK

SCKp cycle time

Note 1

tKCY2

1.8 V

≤ EVDD < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 VNote2

fMCK

≤ 4 MHz

10/fMCK

4.0 V

≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V

tKCY2/2

−

2.7 V

≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V

tKCY2/2

−

SCKp high-/low-level

width

Note 2

tKH2,

tKL2

1.8 V

≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V

tKCY2/2

−

2.7 V

≤ VDD < 5.5 V

1/fMCK + 20

SIp setup time

(to SCKp

↑) Note 3

tSIK2

1.8 V

≤ Vb ≤ 3.3 V

1/fMCK + 30

SIp hold time

(from SCKp

↑) Note 4

tKSI2

1/fMCK + 31

4.0 V

≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

2/fMCK +

120

2.7 V

≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

2/fMCK +

214

Delay time from SCKp

↓ to

SOp output

Notes 2, 5

tKSO2

1.8 V

≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

2/fMCK +

573

(Note, Caution and Remark are listed on the next page.)

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