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SY89876L_0708 Datasheet(PDF) 2 Page - Micrel Semiconductor

Part # SY89876L_0708
Description  3.3V, 2.0GHz ANY DIFFERENTIAL IN-TO-LVDS
PDF  10 Pages
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

SY89876L_0708 Datasheet(HTML) 2 Page - Micrel Semiconductor

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Precision Edge®
SY89876L
Micrel, Inc.
M9999-082407
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package
Operating
Package
Lead
Part Number
Type
Range
Marking
Finish
SY89876LMI
MLF-16
Industrial
876L
Sn-Pb
SY89876LMITR(2)
MLF-16
Industrial
876L
Sn-Pb
SY89876LMG(3)
MLF-16
Industrial
876L with
Pb-Free
Pb-Free bar-line indicator
NiPdAu
SY89876LMGTR(2, 3)
MLF-16
Industrial
876L with
Pb-Free
Pb-Free bar-line indicator
NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
Pin Number
Pin Name
Pin Function
12, 9
IN, /IN
Differential Input: Internal 50ý termination resistors to V
T input. Flexible input accepts any
differential input. See “Input Interface Applications” section.
1, 2, 3, 4
Q0, /Q0
Differential Buffered LVDS Outputs: Divided by 1, 2, 4, 8 or 16. See “Truth Table.”
Q1, /Q1
Unused output pairs must be terminated with 100ý across the different pair.
16, 15, 5
S0, S1, S2
Select Pins: See “Truth Table.” LVTTL/CMOS logic levels. Internal 25ký pull-up resistor.
Logic HIGH if left unconnected (divided by 16 mode.) Input threshold is VCC/2.
6
NC
No Connect.
8
/RESET,
LVTTL/CMOS Logic Levels: Internal 25ký pull-up resistor. Logic HIGH if left unconnected.
/DISABLE
Apply LOW to reset the divider (divided by 2, 4, 8 or 16 mode). Also acts as a disable/enable
function. The reset and disable function occurs on the next high-to-low clock input transition.
Input threshold is VCC/2.
10
VREF-AC
Reference Voltage: Equal to V
CC–1.4V (approx.). Used for AC-coupled applications only.
Decouple the VREF–AC pin with a 0.01µF capacitor. See “Input Interface Applications” section.
11
VT
Termination Center-Tap: For CML or LVDS inputs, leave this pin floating. Otherwise, See
Figures 4a to 4f “Input Interface Applications” section.
7, 14
VCC
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitor.
13
GND, Exposed
Ground. Exposed pad must be connected to the same potential as the GND pin.
pad
PIN DESCRIPTION
13
14
15
16
12
11
10
9
1
2
3
4
8
7
6
5
Q0
/Q0
Q1
/Q1
IN
VT
VREF-AC
/IN
16-Pin MLF® (MLF-16)
/RESET(1)
S2
S1
S0
Outputs
1
0
X
X
Reference Clock (pass through)
1
1
0
0
Reference Clock ÷2
1
1
0
1
Reference Clock ÷4
1
1
1
0
Reference Clock ÷8
1
1
1
1
Reference Clock ÷16
0(1)
X
X
X
Q = LOW, /Q = HIGH
Clock Disable
Note:
1. Reset/Disable function is asserted on the next clock input (IN, /IN)
high-to-low transition.
TRUTH TABLE



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