AD9557SLASHPCBZ datasheet(19/92 Pages) AD

19 / 92 page

Data Sheet

AD9557

Rev. A | Page 19 of 92

TYPICAL PERFORMANCE CHARACTERISTICS

fR = input reference clock frequency; fO = output clock frequency; fSYS = SYSCLK input frequency; fS = internal system clock frequency;

LF = SYSCLK PLL internal loop filter used. AVDD, AVDD3, and DVDD at nominal supply voltage; fS = 786.432 MHz, unless otherwise noted.

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10k

100k

10M

100M

FREQUENCY OFFSET (Hz)

INTEGRATED RMS JITTER (12kHz TO 20MHz): 296fs

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–140

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–110

–100

–90

–80

–70

–60

100

10k

100k

10M

100M

FREQUENCY OFFSET (Hz)

INTEGRATED RMS JITTER (12kHz TO 20MHz): 285fs

Figure 3. Absolute Phase Noise (Output Driver = HSTL),

fR = 19.44 MHz, fO = 622.08 MHz,

DPLL Loop BW = 50 Hz, fSYS = 49.152 MHz Crystal

Figure 5. Absolute Phase Noise (Output Driver = HSTL),

fR = 19.44 MHz, fO = 693.482991 MHz,

DPLL Loop BW = 50 Hz, fSYS = 49.152 MHz Crystal

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

100

10k

100k

10M

100M

FREQUENCY OFFSET (Hz)

INTEGRATED RMS JITTER (12kHz TO 20MHz): 320fs

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

100

10k

100k

10M

100M

FREQUENCY OFFSET (Hz)

INTEGRATED RMS JITTER (12kHz TO 20MHz): 301fs

Figure 4. Absolute Phase Noise (Output Driver = HSTL),

fR = 19.44 MHz, fO = 644.53125 MHz,

DPLL Loop BW = 50 Hz, fSYS = 49.152 MHz Crystal

Figure 6. Absolute Phase Noise (Output Driver = HSTL),

fR = 19.44 MHz, fO = 174.703 MHz,

DPLL Loop BW = 1 kHz, fSYS = 49.152 MHz Crystal

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