ADL5336ACPZ-R7 datasheet(4/32 Pages) AD

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ADL5336

Data Sheet

Rev. B | Page 4 of 32

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

f = 350 MHz

Noise Figure

VGA1, Gain Code 00, VGAIN = 1 V

VGA2, Gain Code 11, VGAIN = 1 V

7.7

Output IP3

VGA1, Gain Code 00, VGAIN = 1 V

12 (19)

dBV (dBm)

OutputVoltage Level of 1.0V p-p

VGA1, Gain Code 11, VGAIN = 1 V

10.5(17.5)

dBV (dBm)

VGA2, Gain Code 00, VGAIN = 1 V

18 (28)

dBV (dBm)

VGA2, Gain Code 11, VGAIN = 1 V

16 (26)

dBV (dBm)

Output P1dB

VGA1, Gain Code 00, VGAIN = 1 V

0 (7)

dBV (dBm)

VGA1, Gain Code 11, VGAIN = 1 V

0 (7)

dBV (dBm)

VGA2, Gain Code 00, VGAIN = 1 V

−1.5 (+8.5)

dBV (dBm)

VGA2, Gain Code 11, VGAIN = 1 V

−1.5 (+8.5)

dBV (dBm)

SQUARE LAW DETECTORS

DTO1, DTO2

Output Setpoint

SPI controlled, 3 dB steps

−24

−3

dBV

Output Range

0.1

VS/2

AGC Step Response Range

5 dB input step, CAGC = 0.1 µF

1.5

DIGITAL LOGIC

LE, CLK, DATA, SDO

Input High Voltage, VINH

>2.2

Input Low Voltage, VINL

<1.8

Input Current, IINH/IINL

µA

Input Capacitance, CIN

SPI TIMING

LE, CLK, DATA, SDO

fCLK

MHz

tDH

DATA hold time

tDS

DATA setup time

tLH

LE hold time

tLS

LE setup time

tPW

CLK high pulse width

CLK-to-SDO delay

POWER AND ENABLE

VPOS, VPSD, COM, COMD, ENBL

Supply Voltage Range

4.5

5.5

Total Supply Current

ENBL = 5 V

Disable Current

ENBL = 0 V

Disable Threshold

2.3

Enable Response Time

Delay following low-to-high transition until

device meets full specifications in VGA mode

800

Disable Response Time

Delay following high-to-low transition until

device produces full attenuation in VGA mode

ADL5336ACPZ-R7 Datasheet(PDF) 4 Page - Analog Devices

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