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MPC8378E Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
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MPC8378E Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
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2 / 128 page  MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8 2 Freescale Semiconductor controller, dual I2C controllers, a 4-channel DMA controller, an enhanced secured digital host controller, and a general-purpose I/O port. This figure shows the block diagram of the chip. Figure 1. MPC8378E Block Diagram and Features The following features are supported in the chip: • e300c4s core built on Power Architecture® technology with 32 KB instruction cache and 32 KB data cache, a floating point unit, and two integer units • DDR1/DDR2 memory controller supporting a 32/64-bit interface • Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MHz operation • 32-bit local bus interface running up to 133-MHz • USB 2.0 (full/high speed) support • Power management controller for low-power consumption • High degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration • Optional security engine provides acceleration for control and data plane security protocols The optional security engine (SEC 3.0) is noted with the extension “E” at the end. It allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms. MPC8378E DMA PCI Security Enhanced e300 Core 32 KB I-Cache 32 KB D-Cache DUART Dual I2C Timers GPIO SPI Interrupt Controller DDR1/DDR2 SDRAM Controller Local Bus SD/MMC Controller USB 2.0 Hi-Speed Host Device eTSEC SGMII, RGMII, RMII, RTBI, MII eTSEC SGMII, RGMII, RMII, RTBI, MII PCI Express x1 x2 |
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