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CSSTV32852GKFREP Datasheet(PDF) 4 Page - Texas Instruments |
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CSSTV32852GKFREP Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 10 page ![]() www.ti.com RECOMMENDED OPERATING CONDITIONS (1) ELECTRICAL CHARACTERISTICS SN74SSTV32852-EP 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES700 – OCTOBER 2007 MIN NOM MAX UNIT VCC Supply voltage VDDQ 2.7 V VDDQ Output supply voltage 2.3 2.7 V VREF Reference voltage (VREF = VDDQ/2) 1.15 1.25 1.35 V VTT Termination voltage VREF – 40 mV VREF VREF + 40 mV V VI Input voltage 0 VCC V VIH AC high-level input voltage Data inputs VREF + 310 mV V VIL AC low-level input voltage Data inputs VREF – 310 mV V VIH DC high-level input voltage Data inputs VREF + 150 mV V VIL DC low-level input voltage Data inputs VREF – 150 mV V VIH High-level input voltage RESET 1.7 V VIL Low-level input voltage RESET 0.7 V VICR Common-mode input voltage range CLK, CLK 0.97 1.53 V VI(PP) Peak-to-peak input voltage CLK, CLK 360 mV IOH High-level output current –20 mA IOL Low-level output current 20 TA Operating free-air temperature -40 85 °C (1) The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT VIK II = –18 mA 2.3 V –1.2 V IOH = –100 μA 2.3 V to 2.7 V VDDQ – 0.2 V VOH IOH = –16 mA 2.3 V 1.95 IOL = 100 μA 2.3 V to 2.7 V 0.2 V VOL IOL = 16 mA 2.3 V 0.35 II All inputs VI = VCC or GND 2.7 V ±5 μA Static standby RESET = GND IO = 0 10 μA ICC 2.7 V Static operating RESET = VCC, VI= VIH(AC) or VIL(AC) 35 mA RESET = VCC, VI = VIH(AC) or VIL(AC), IO = 0 Dynamic operating – μA/ CLK and CLK switching 50% duty 46 clock only MHz cycle RESET = VCC, VI = VIH(AC) or VIL(AC), ICCD 2.7 V μA/ CLK and CLK switching 50% duty Dynamic operating – clock cycle, one data input switching at 12 per each data input MHz/ one-half clock frequency, 50% duty D input cycle rOH Output high IOH = –20 mA 2.3 V to 2.7 V 7 20 Ω rOL Output low IOL = 20 mA 2.3 V to 2.7 V 7 20 Ω Data inputs VI = VREF ± 310 mV 3 3.75 4.25 CI CLK, CLK VICR = 1.25 V, VI(PP) = 360 mV 2.5 V 3 3.5 4 pF RESET VI = VCC or GND 3.5 4.35 5 (1) All typical values are at VCC = 2.5 V, TA = 25°C. 4 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTV32852-EP |
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