1

FEATURES

DESCRIPTION/ORDERING INFORMATION

SN74SSTV32852-EP

24-BIT TO 48-BIT REGISTERED BUFFER

WITH SSTL_2 INPUTS AND OUTPUTS

SCES700 – OCTOBER 2007

www.ti.com

2

• Controlled Baseline

• Supports SSTL_2 Data Inputs

–

One Assembly/Test Site, One Fabrication

• Outputs Meet SSTL_2 Class II Specifications

Site

• Differential Clock (CLK and CLK) Inputs

• Extended Temperature Performance of –40°C

• Supports LVCMOS Switching Levels on the

to 85

°C

RESET Input

• Enhanced Diminishing Manufacturing Sources

• RESET Input Disables Differential Input

(DMS) Support

Receivers, Resets All Registers, and Forces

• Enhanced Product-Change Notification

All Outputs Low

• Pinout Optimizes DIMM PCB Layout

• Member of the Texas Instruments Widebus™

• One Device Per DIMM Required

Family

• Latch-Up Performance Exceeds 100 mA Per

• 1-to-2 Outputs Support Stacked DDR DIMMs

JESD 78, Class II

(1)

Component qualification in accordance with JEDEC and

• ESD Protection Exceeds JESD 22

industry standards to ensure reliable operation over an

–

2000-V Human-Body Model (A114-A)

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

–

1000-V Charged-Device Model (C101)

temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.

The SN74SSTV32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing of

CLK going high and CLK going low.

The device supports low-power standby operation. When RESET is low, the differential input receivers are

RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must be

held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the

low state during power up.

ORDERABLE PART NUMBER

TOP-SIDE MARKING

–40

°C to 85°C

LFBGA – GKF

Tape and reel

CSSTV32852GKFREP

SV852IEP

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/packaging.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.