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ST10F272B Datasheet(PDF) 93 Page - STMicroelectronics |
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ST10F272B Datasheet(HTML) 93 Page - STMicroelectronics |
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93 / 188 page ![]() ST10F272B/ST10F272E System reset Doc ID 11917 Rev 3 93/188 Figure 20. Synchronous short / long hardware RESET (EA = 1) 1. RSTIN assertion can be released there. Refer also to Section 21.1 for details on minimum pulse duration. 2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5 V for 5 V operation), the asynchronous reset is then immediately entered. 3. 3. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after reset. 4. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 21.1). |
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