ST10F272B_12 datasheet(97/188 Pages) STMICROELECTRONICS

97 / 188 page

ST10F272B/ST10F272E

System reset

Doc ID 11917 Rev 3

97/188

20.5

Watchdog timer reset

When the watchdog timer is not disabled during the initialization, or serviced regularly

during program execution, it overflows and trigger the reset sequence.

Unlike hardware and software resets, the watchdog reset completes a running external bus

cycle if this bus cycle either does not use READY, or if READY is sampled active (low) after

the programmed wait states.

When READY is sampled inactive (high) after the programmed wait states the running

external bus cycle is aborted. Then the internal reset sequence is started.

Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0.7...P0.2 are cleared

(that is written at ‘1’).

A Watchdog reset is always taken as synchronous: there is no influence on Watchdog Reset

behavior with RPD status. In case Bidirectional Reset is selected, a Watchdog Reset event

pulls RSTIN pin low: this occurs only if RPD is high; if RPD is low, RSTIN pin is not pulled

low even though Bidirectional Reset is selected.

Refer to Figure 24 and Figure 25 for unidirectional SW reset timing, and to Figure 26,

Figure 27 and Figure 28 for bidirectional.

Figure 24.

SW / WDT unidirectional RESET (EA = 1)

ST10F272B Datasheet(PDF) 97 Page - STMicroelectronics