ST10F280_12 datasheet(222/239 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F280

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Doc ID 8673 Rev. 3

20.4.11

Demultiplexed bus

VDD = 5 V ± 10%, VSS = 0 V, TA = -40°C to 125°C, CL = 50 pF,

ALE cycle time = 4 TCL + 2tA + tC + tF (50 ns at 40 MHz CPU clock without wait states).

Table 49.

Demultiplexed bus characteristics

Symbol

Parameter

Maximum CPU Clock

= 40MHz

Variable CPU Clock

1/2 TCL = 1 to 40MHz

Min.

Max.

Min.

Max.

CC ALE high time

4 + tA

–TCL - 8.5 + tA

–ns

CC Address setup to ALE

2 + tA

–

TCL - 10.5 + tA

–ns

t80 CC

Address/Unlatched CS

setup to RD, WR (with

R/W-delay)

16.5 + 2tA

–

2 TCL - 8.5 +

2tA

–ns

t81 CC

Address/Unlatched CS

setup to RD, WR (no R/W-

delay)

4 + 2tA

–

TCL - 8.5 + 2tA

–ns

t12 CC

RD, WR low time (with

R/W-delay)

15.5 + tC

–

2 TCL - 9.5 +

–ns

t13 CC

RD, WR low time (no R/W-

delay)

28 + tC

–

3 TCL - 9.5 +

–ns

t14 SR

RD to valid data in (with

R/W-delay)

–6 + tC

–

2 TCL - 19 + tC ns

t15 SR

RD to valid data in (no

R/W-delay)

–

18.5 + tC

–

3 TCL - 19 + tC ns

t16 SR ALE low to valid data in

–

18.5 + tA +

–

3 TCL - 19

+ tA + tC

t17 SR

Address/Unlatched CS to

valid data in

–

22 + 2tA +

–

4 TCL - 28

+ 2tA + tC

t18 SR

Data hold after RD rising

edge

0–

–

t20 SR

Data float after RD rising

edge (with R/W-delay) (1)(2)

–16.5 + tF

–

2 TCL - 8.5

+ tF + 2tA

t21 SR

Data float after RD rising

edge (no R/W-delay) (1)(2)

–4 + tF

–

TCL - 8.5

+ tF + 2tA

t22 CC Data valid to WR

10 + tC

–

2 TCL - 15 + tC

–ns

t24 CC Data hold after WR

4 + tF

–TCL - 8.5 + tF

–ns

t26 CC

ALE rising edge after RD,

-10 + tF

–-10 + tF

–ns

t28 CC

Address/Unlatched CS

hold after RD, WR (3)

0 (no tF)

-5 + tF

(tF > 0)

–

0 (no tF)

-5 + tF

(tF > 0)

–ns

t28h CC

Address/Unlatched CS

hold after WRH

-5 + tF

–-5 + tF

–ns

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