Introduction

STi5267

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Doc ID 16950 Rev 1

1.1.2

QAM demodulation

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Decodes ITU-T J.83-Annexes A/C and DVB-C bit streams

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High-performance integrated ADC for direct IF architecture in all QAM modes

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Supports 16, 32, 64, 128 and 256 point constellations

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Variable symbol rates

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Front derotator for better low symbol rate performance and relaxed tuner constraints

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Integrated matched filtering

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Robust integrated adaptive pre- and post- high multi-tap equalizer

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On-chip FEC A/C with ability to bypass individual blocks

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Built-in clock management for operation from a flexible 4 MHz to 30 MHz external

reference

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Fast signal acquisition

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ADC for RF signal strength indicator

1.1.3

Interfaces

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I²C serial bus interface:

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Fast, up to 400 kHz slave interface

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Four possible slave addresses

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Flexible and DVB-CI compliant TS output

1.1.4

Processor core

The STi5267 integrates a 450 MHz ST40-300 processor core that features a 32-bit

superscalar RISC CPU and IEEE-754 compliant floating point unit (FPU). The ST40-300

includes two-way, set-associative caches and an interrupt controller with 15 user interrupt

sources and an interrupt expansion port.

1.1.5

External memory interface (EMI)

The EMI is a general-purpose interface for attaching Flash memory and peripherals. The

EMI features are:

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Five banks

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Addressing up to at least 64 Mbytes of NOR Flash

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External bus master support through BUSREQ/BUSGNT signals

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Slave Mode EMI support

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Single level cell (SLC) NAND Flash and boot from SLC NAND Flash

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Serial Flash support

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PCI interface, host and device selected on boot

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ATAPI PIO mode 4

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DVB-CI+

1.1.6

Local memory interface (LMI)

The STi5267 integrates one 16-bit DDR2-DDR1 interface. The interface can run up to

400 MHz when configured in DDR2 mode or up to 250 MHz when in DDR1 mode.