Introduction

STiH207

2/4

Doc ID 022309 Rev 1

1

Introduction

The STiH207 offers current users of ST’s growing family of advanced decoding ICs

enhancements in performance and features, enabling operators to offer consumers new

multimedia-rich services and viewing experiences, including new 3DTV features. Faster

DDR3 memory is also supported, and the applications CPU benefits from an L2 cache. The

STiH207 keeps pace with the latest advanced security requirements of the main CA

vendors, and an integrated standby controller enables the STiH207 to target stringent low

power regulations.

Features

Benefits

ST40 applications CPU, with 32KI and 32KD L1

caches and 256K L2 cache.

for applications and middleware.

1.

Frequency for extended mode to be confirmed after silicon characterization.

Integrated low power standby controller within its

own power island.

Secure hibernation to, and fast resume from, very

low power passive standby mode, targeting STB

standby power < 0.5 W.

Latest generation of ST's Delta video decoder

with an ST231-based multi-codec capable

controller, coupled with a High Quality Video

Display Pipeline (HQVDP).

Decoding of advanced high definition standards

(MPEG2, H264, VC-1, AVS) plus the performance

and flexibility for web-based content decoding such

impacting applications CPU performance.

Dual USB 2.0 hosts, eSATA, Ethernet MAC with

MII/RMII/TMII interfaces, PCI-e, SD-MMC/SDIO

interface.

Extensive high speed connectivity for the widest

range of STB peripherals, such as Flash drives,

external HDDs, Ethernet, home network controllers

memory cards.

Decoding of 1080p60 AVC, dual HD AVC and

MVC SHP video streams.

Enables advanced high-definition viewing

experiences including full resolution per eye 3DTV,

full-HD 2D services and HD picture-in-picture

support (HD-PIP).

NOCS1.0/1.1/1.2/3.0, NSK2.0 and DVB-CSA3

ready.

Fully compliant with the latest advanced security

requirements of CA vendors.