PXD10 datasheet(24/130 Pages) FREESCALE

24 / 130 page

Overview

PXD10 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

– Support for frequency ramping from PLL

— The primary FMPLL module is for use as a system clock source. The auxiliary FMPLL is

available for use as an alternate, modulated or non-modulated clock source to eMIOS modules

and as alternate clock to the DCU for pixel clock generation.

•

The main oscillator provides the following features:

— Input frequency range 4–16 MHz

— Square-wave input mode

— Oscillator input mode 3.3 V (5.0 V)

— Automatic level control

— PLL reference

•

PXD10 includes a 32 KHz low power external oscillator for slow execution, low power, and Real

Time Clock

•

Dedicated internal 128 kHz RC oscillator for low power mode operation and self wake-up

— ±10% accuracy across voltage and temperature (after factory trimming)

— Trimming registers to support improved accuracy with in-application calibration

•

Dedicated 16 MHz internal RC oscillator

— Used as default clock source out of reset

— Provides a clock for rapid start-up from low power modes

— Provides a back-up clock in the event of PLL or External Oscillator clock failure

— Offers an independent clock source for the Watchdog timer

— ±5% accuracy across voltage and temperature (after factory trimming)

— Trimming registers to support frequency adjustment with in-application calibration

1.6.26

Crossbar Switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and

four slave ports. The crossbar supports a 32-bit address bus width and a 32-bit data bus width.

The crossbar allows four concurrent transactions to occur from any master port to any slave port but one

of those transfers must be an instruction fetch from internal flash. If a slave port is simultaneously

requested by more than one master port, arbitration logic selects the higher priority master and grants it

ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority

master completes its transactions. Requesting masters having equal priority are granted access to a slave

port in round-robin fashion, based upon the ID of the last master to be granted access.

The crossbar provides the following features:

•

Four master ports

— e200z0h core instruction port

— e200z0h core complex load/store data port

— eDMA controller

— Display control unit

PXD10 Datasheet(PDF) 24 Page - Freescale Semiconductor, Inc

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