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CY8C54LP Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY8C54LP Datasheet(HTML) 8 Page - Cypress Semiconductor |
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8 / 117 page  PRELIMINARY PSoC® 5LP: CY8C54LP Family Datasheet Document Number: 001-84934 Rev. ** Page 8 of 117 Figure 2-5 and Figure 2-6 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog performance on a 2-layer board. The two pins labeled VDDD must be connected together. The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-5 and Power System on page 25. The trace between the two VCCD pins should be as short as possible. The two pins labeled VSSD must be connected together. For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board Layout Considerations for PSoC® 3 and PSoC 5. Figure 2-5. Example Schematic for 100-Pin TQFP Part with Power Connections Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-6. VSSB 10 IND 11 VBOOST 12 VBAT 13 VSSD 14 XRES 15 VCCA 63 VSSA 64 VDDA 65 VSSD 66 SIO, P12[2] 67 SIO, P12[3] 68 P4[0] 69 P4[1] 70 OA2OUT, P0[0] 71 OA0OUT, P0[1] 72 OA0+, SAR1REF, P0[2] 73 OA0-, REF0, P0[3] 74 VDDIO0 75 P5[0] 16 P5[1] 17 P5[2] 18 P5[3] 19 P1[0], SWDIO, TMS 20 P1[1], SWDCK, TCK 21 P1[2] 22 P1[3], SWV, TDO 23 P1[4], TDI 24 P1[5], NTRST 25 P6[7] 9 P2[5] 1 P2[6] 2 P2[7] 3 P12[4], SIO 4 P12[5], SIO 5 P6[4] 6 P6[5] 7 P6[6] 8 OA1OUT, P3[6] 51 OA3OUT, P3[7] 52 SIO, P12[0] 53 SIO, P12[1] 54 KHZXOUT, P15[2] 55 KHZXIN, P15[3] 56 NC 57 NC 58 NC 59 NC 60 NC 61 NC 62 VSSD VDDA VCCA VSSD VSSA VSSA VSSD VSSD VSSD VSSD 0.1 UF C8 VSSD VDDD VDDD VDDD VDDD VDDD VSSD 1 UF C9 0.1 UF C10 0.1 UF C11 0.1 UF C16 0.1 UF C12 0.1 UF C6 0.1 UF C2 1 UF C15 1 UF C1 VSSD VDDD VSSD VDDA VSSD VCCD 1 UF C17 VSSA VDDA |
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